Convert integer to a vector in VHDL

[crayon lang=”VHDL”]

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

architecture structural of is

(…)

signal segm_vector: std_logic_vector(6 downto 0);
signal int_vector: std_logic_vector(3 downto 0);
signal int_counter: integer;

begin
— convert the int from the counter to a vector

lbl2: counter port map (clk, ‘1’, int_counter);

int_vector <= conv_std_logic_vector(int_counter, 4); -- put the vector into the segment decoder lbl1: segm_dec port map (int_vector, segm_vector); end structural; [/crayon]